1. Field of the Invention
The present invention relates generally to circuit boards used in information handling systems. More specifically, the present invention provides a method and apparatus for improving performance in conductor traces used in circuit boards in information handling systems.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
As computers have increased in performance, it has become necessary to use higher data bit rates in high-density circuitry with minimal spacing between the various circuit conductors. As a result, it has become difficult to fabricate circuit boards that meet the needs of high performance computing technology using conventional circuit board manufacturing methods. The necessity for a more ideal transmission path vital to higher-performance electrical signals is in direct conflict with the minimization of both cost and size.
Many of today's high speed busses require routed signals to travel from source to destination with minimal skew introduced by the interconnect. The process by which this is achieved is called “length matching” where any two or more signals are routed through conductors having the same physical length from source to destination. This practice is also becoming more commonplace on the chip package substrate.
One method for trace length matching is called “serpentining,” wherein extra length is added to signals that have a shorter physical distance from point A to B than their counterparts. Generally, due to the limited amount of routing real estate available, most serpentine routes are “tight” in that these parallel trace segments are spaced at a distance two to three times the width of the trace. One problem with this approach is that a serpentine trace does not have the same “electrical length” as a straight trace of equivalent physical length. As used herein, “electrical length” will be understood by those of skill in the art to refer to the electrical transmission characteristics of a straight conductor having a predetermined width and length. With regard to the “electrical length” of a serpentine-pattern conductor, even though serpentine trace contains the same length of conductor material as a straight trace, it does not exhibit the same electrical transmission properties; therefore, it does not have the same “electrical length” as the straight trace for purposes of “length matching” to control skew and other signal propagation issues. The mutual inductance and capacitance of the parallel segments creates a self-coupling mechanism which causes a signal on a serpentine trace to propagate faster than it would otherwise on a straight trace. Another problem with this approach is that a serpentine consumes significantly more routing real estate than a straight trace.
Prior methods for altering the electrical length of a trace have been limited to: 1) making the trace physically longer; 2) adding discrete components such as series resistors, capacitors or vias to slow the edge rate, thereby increasing flight time; and 3) routing some combination of stripline and microstrip materials which have different propagation delay characteristics for an equivalent length of trace.
The problems inherent in these approaches relate to the tradeoffs required to achieve the desired results. Lengthening traces beyond a certain point without introducing coupling problems or utilizing more space may not be an option for compact designs. This is especially true for chip package substrate routing. Adding discrete components can create lumped impedance discontinuities and degrade signal slew rates. In view of the shortcomings of the prior art, there is a need for an improved method and apparatus for altering the effective electrical length of trace on a circuit board.